Asynchronous Pulse Logic

Nyström, 2001

Category: EE

Overall Rating

3.4/5 (24/35 pts)

presents a unique asynchronous design methodology based on engineered pulse timings
offering a different trade-off than strict QDI or bundled data.
modern formal verification and simulation tools offer a plausible path to address the core robustness concerns regarding its timing assumptions.
potentially enabling its use in designing reliable digital control logic for niche pulse-based systems, such as the interfaces needed in large-scale neuromorphic hardware.

bridging the gap between strictly delay-insensitive QDI and simplified bundled-data logic by introducing controlled timing assumptions focused on engineered pulse properties
using engineered pulses within a single-track handshake framework to simplify control logic compared to QDI's complex completion circuitry
The detailed circuit templates developed around these pulsed signals, and the formal theory attempting to link analog pulse properties (shape, dynamics) to digital correctness, hold potential.
could be particularly valuable in the context of modern large-scale neuromorphic computing

introducing carefully controlled timing assumptions—undermined a key benefit of more robust asynchronous design (like QDI) without fully overcoming the complexities it inherited from dynamic logic.
reliance on analog timing properties (pulse length, setup/hold times) makes STAPL circuits brittle across different process corners, supply voltages, and temperatures
The synthesis flow via PL1 to PRS is described as heuristic and incomplete
Attempting to apply a timing-dependent digital pulse logic like STAPL to domains like spiking neural networks... would likely be inefficient and misguided

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