Throughput Optimization of Quasi Delay Insensitive Circuits via Slack Matching

, 2008

Category: EE

Overall Rating

2.3/5 (16/35 pts)

This paper presents a method to optimize throughput in Quasi Delay-Insensitive circuits by modeling them with repetitive Event-Rule systems and formulating buffer insertion as a Mixed Integer Linear Program.
...its core techniques and detailed modeling elements are highly specialized to the properties and formalisms of QDI circuits.
This makes the method difficult to translate directly and actionably to other domains without extensive re-modeling effort...
...offering limited unique, actionable paths for modern research outside its niche...

The core idea of formally modeling system dependencies and timing constraints (using Event-Rule systems and constraint graphs) to systematically optimize throughput via resource insertion (slack matching buffers) has significant latent potential.
The detailed breakdown of how buffer insertion affects critical paths in this formal graph model provides a blueprint for analyzing resource impact in analogous systems.
The concepts are highly applicable outside asynchronous circuit design. Many complex systems can be viewed as a network of processing stages with dependencies and communication delays, where adding "buffers" (resources like queue capacity, inventory, redundant servers) can improve throughput but adds cost.
Modern machine learning, specifically reinforcement learning or graph neural networks, could be trained to explore the vast design space of buffer placements, potentially guided by the critical cycle analysis and MILP structure derived in the thesis, leading to far more effective heuristics than previously feasible.

The paper's core focus on optimizing Quasi Delay-Insensitive (QDI) asynchronous circuits is its primary vulnerability in a modern context.
This paper likely faded into obscurity because its methods are deeply tied to a non-mainstream design style and face practical scalability challenges compared to established synchronous techniques.
The paper relies on a very specific formal model (ER systems derived from HSE/PRS with restrictions like stable disjuncts and four-phase handshakes, simplified assumptions about buffer properties). It explicitly excludes circuits with "unstable disjuncts" or complex initializations...
Modern EDA tools for synchronous design incorporate sophisticated buffering, retiming, and placement optimizations that are tightly integrated into the physical design flow and operate on standard HDL inputs. While these tools don't apply to QDI circuits directly, they solve the analogous performance optimization problems effectively for the dominant design paradigm.

Ignore