Soft-error Tolerant Quasi Delay-insensitive Circuits

Jang, 2008

Category: EE

Overall Rating

2.9/5 (20/35 pts)

This paper presents a unique, async-native approach to soft-error tolerance by integrating local error correction into the circuit structure using duplicated logic and cross-coupled elements (DD scheme) and robust asynchronous communication codes (EDDI).
While the presented area and performance overheads limit general applicability and require significant re-assessment for modern process nodes...
...these specific techniques could be uniquely suited for highly distributed, asynchronous computing fabrics where global error management is infeasible, such as certain neuromorphic architectures.

The core ideas center around integrating fault tolerance directly into the asynchronous communication protocols and gate-level design, leveraging the unique properties of QDI circuits (stability, local handshaking, completion detection) for error recovery without a global clock or complex post-computation voting/correction logic for general logic.
The Duplicated Double-Checking (DD) scheme... and the concept of Error Detecting Delay-Insensitive (EDDI) codes... offer a fundamentally different approach to handling transient faults compared to traditional synchronous methods.
The concepts are highly applicable to any computing or communication system that is asynchronous, event-driven, or distributed with variable latency, where traditional synchronous fault tolerance is difficult or inefficient.
This thesis offers a potent, unconventional foundation for designing fault-tolerant neuromorphic hardware.

The core assumption of the target domain – mainstream QDI asynchronous design – has not materialized as predicted.
Modern process nodes (sub-20nm) exhibit different error mechanisms... potentially rendering the proposed DD scheme and its specific parameterizations less effective or requiring significant, non-trivial re-engineering.
The high overheads presented in the thesis likely contributed significantly to its limited impact and subsequent obscurity in the broader digital design community.
The paper explicitly states area penalties of 2-3x for random logic and up to 4x for memory... coupled with a throughput reduction of 40-50%...

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