Testing Delay-Insensitive Circuits

Hazewindus, 1992

Category: VLSI

Overall Rating

2.0/5 (14/35 pts)

This paper presents a model-based, behavioral fault analysis technique tied to a specific formal synthesis method for niche delay-insensitive circuits.
While the concept of analyzing behavioral fault impact from formal models is relevant to testing concurrent systems, the paper's specific techniques, fault models (stuck-at), and reliance on a non-mainstream design paradigm severely limit its direct applicability to modern hardware or software challenges.
It is more of a historical artifact for a specific research path than a source of immediately actionable modern research directions.

The core idea is testing asynchronous circuits, which are not mainstream today but are gaining renewed interest for specialized applications (AI accelerators, secure hardware, low-power design).
The methodology is deeply tied to formal methods (CSP, production rules, handshaking expansion) and models faults by their behavioral effect on these formal rules (inhibiting/stimulating transitions, causing halting).
Applying the same fault models (perturbations to state transitions or communication events) and analysis techniques... to formally specified concurrent software modules or network protocols.
Modern advances in... Highly efficient SAT/SMT solvers, model checkers, and automated theorem provers are vastly more powerful now than in 1992.

The fundamental assumption underpinning this thesis is the widespread practical implementation of pure delay-insensitive (DI) circuits... which proved to be niche.
The proposed testing methods... faced significant practical disadvantages compared to established synchronous test techniques like scan chains.
The thesis's technical framework relies heavily on the "handshaking expansion" and "production rule set"... making the test generation algorithms... highly coupled to this specific representation, lacking portability.
Current testing methodologies for digital circuits are overwhelmingly focused on synchronous designs... The core problem this thesis tackled... has been largely bypassed by the industry's pivot.

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